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Features
* * * * * * * * * * * * * * * * *
Operating Range from 5V to 27V Baud Rate up to 20 Kbaud Improved Slew Rate Control According to LIN Specification 2.0, 2.1 and SAEJ2602-2 Fully Compatible with 3.3V and 5V Devices Dominant Time-out Function at Transmit Data (TXD) Normal and Sleep Mode Wake-up Capability via LIN Bus (90 s Dominant) External Wake-up via WAKE Pin (35 s Low Level) Control of External Voltage Regulator via INH Pin Very Low Standby Current During Sleep Mode (10 A) Wake-up Source Recognition Bus Pin Short-circuit Protected versus GND and Battery LIN Input Current < 2 A if VBAT Is Disconnected Overtemperature Protection High EMC Level Interference and Damage Protection According to ISO/CD 7637 Fulfills the OEM "Hardware Requirements for LIN in Automotive Applications Rev.1.0"
LIN Transceiver ATA6662 ATA6662C
1. Description
The ATA6662 is a fully integrated LIN transceiver complying with the LIN specification 2.0, 2.1 and SAEJ2602-2. It interfaces the LIN protocol handler and the physical layer. The device is designed to handle the low-speed data communication in vehicles, for example, in convenience electronics. Improved slope control at the LIN bus ensures secure data communication up to 20 Kbaud with an RC oscillator for protocol handling. Sleep Mode guarantees minimal current consumption. The ATA6662 has advanced EMI and ESD performance. Figure 1-1. Block Diagram
7 Receiver RXD 1 VS
+
Filter
6
LIN
Wake-up bus timer
Short-circuit and overtemperature protection
TXD
4
TXD time-out timer VS
Slew rate control
VS Control unit Wake-up timer Sleep mode 5 GND
WAKE
3
2 EN
8 INH
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2. Pin Configuration
Figure 2-1. Pinning SO8
RXD EN WAKE TXD 1 2 3 4 8 7 6 5 INH VS LIN GND
Table 2-1.
Pin 1 2 3 4 5 6 7 8
Pin Description
Symbol RXD EN WAKE TXD GND LIN VS INH Function Receive data output (open drain) Enables Normal Mode; when the input is open or low, the device is in Sleep Mode High voltage input for local wake-up request. If not needed, connect directly to VS Transmit data input; active low output (strong pull-down) after a local wake-up request Ground, heat sink LIN bus line input/output Battery supply Battery-related inhibit output for controlling an external voltage regulator; active high after a wake-up request
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3. Functional Description
3.1 Physical Layer Compatibility
Since the LIN physical layer is independent from higher LIN layers (e.g., the LIN protocol layer), all nodes with a LIN physical layer according to revision 2.x can be mixed with LIN physical layer nodes, which, according to older versions (i.e., LIN 1.0, LIN 1.1, LIN 1.2, LIN 1.3), are without any restrictions.
3.2
Supply Pin (VS)
Undervoltage detection is implemented to disable transmission if VS falls to a value below 5V in order to avoid false bus messages. After switching on VS, the IC switches to Fail-safe Mode and INHIBIT is switched on. The supply current in Sleep Mode is typically 10 A.
3.3
Ground Pin (GND)
The ATA6662 does not affect the LIN Bus in the case of a GND disconnection. It is able to handle a ground shift up to 11.5% of VS.
3.4
Bus Pin (LIN)
A low-side driver with internal current limitation and thermal shutdown and an internal pull-up resistor are implemented as specified for LIN 2.x. The voltage range is from -27V to +40V. This pin exhibits no reverse current from the LIN bus to VS, even in the case of a GND shift or VBatt disconnection. The LIN receiver thresholds are compatible to the LIN protocol specification.The fall time (from recessive to dominant) and the rise time (from dominant to recessive) are slope controlled. The output has a self-adapting short circuit limitation; that is, during current limitation, as the chip temperature increases, the current is reduced.
3.5
Input/Output Pin (TXD)
In Normal Mode the TXD pin is the microcontroller interface to control the state of the Lin output. TXD must be at Low- level in order to have a low LIN Bus. If TXD is high, the LIN output transistor is turned off and the Bus is in recessive state. The TXD pin is compatible to both a 3.3V or 5V supply. During fail-safe Mode, this pin is used as output and is signalling the wake-up source (see Section 3.14 "Wake-up Source Recognition" on page 7). It is current limited to < 8 mA.
3.6
TXD Dominant Time-out Function
The TXD input has an internal pull-down resistor. An internal timer prevents the bus line from being driven permanently in dominant state. If TXD is forced to low longer than tDOM > 6 ms, the pin LIN will be switched off (Recessive Mode). To reset this mode, switch TXD to high (> 10 s) before switching LIN to dominant again.
3.7
Output Pin (RXD)
This pin reports to the microcontroller the state of the LIN bus. LIN high (recessive) is reported by a high level at RXD, LIN low (dominant) is reported by a low voltage at RXD. The output is an open drain, therefore, it is compatible to a 3.3V or 5V power supply. The AC characteristics are defined with a pull-up resistor of 5 k to 5V and a load capacitor of 20 pF. The output is shortprotected. In Unpowered Mode (VS = 0V), RXD is switched off. For ESD protection a Zener diode is integrated, with VZ = 6.1V.
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3.8
Enable Input Pin (EN)
This pin controls the Operation Mode of the interface. If EN = 1, the interface is in Normal Mode, with the transmission path from TXD to LIN and from LIN to RXD both active. At a falling edge on EN, while TXD is already set to high, the device is switched to Sleep Mode and no transmission is possible. In Sleep Mode, the LIN bus pin is connected to VS with a weak pull-up current source. The device can transmit only after being woken up (see Section 3.9, "Inhibit Output Pin (INH)" ). During Sleep Mode the device is still supplied from the battery voltage. The supply current is typically 10 A. The pin EN provides a pull-down resistor in order to force the transceiver into Sleep Mode in case the pin is disconnected.
3.9
Inhibit Output Pin (INH)
This pin is used to control an external switchable voltage regulator having a wake-up input. The inhibit pin provides an internal switch towards pin VS. If the device is in Normal Mode, the inhibit high-side switch is turned on and the external voltage regulator is activated. When the device is in Sleep Mode, the inhibit switch is turned off and disables the voltage regulator. A wake-up event on the LIN bus or at pin WAKE will switch the INH pin to the VS level. After a system power-up (VS rises from zero), the pin INH switches automatically to the VS level.
3.10
Wake-up Input Pin (WAKE)
This pin is a high-voltage input used to wake the device up from Sleep Mode. It is usually connected to an external switch in the application to generate a local wake-up. A pull-up current source with typically -10 A is implemented. The voltage threshold for a wake-up signal is 3V below the VS voltage with an output current of typically -3 A. If you do not need a local wake-up in your application, connect pin WAKE directly to pin VS.
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3.11 Operation Modes
1. Normal Mode This is the normal transmitting and Receiving Mode. All features are available. 2. Sleep Mode In this mode the transmission path is disabled and the device is in low power mode. Supply current from VBatt is typically 10 A. A wake-up signal from the LIN bus or via pin WAKE will be detected and will switch the device to Fail-safe Mode. If EN then switches to high, Normal Mode is activated. Input debounce timers at pin WAKE (tWAKE), LIN (tBUS) and EN (tsleep,tnom) prevent unwanted wake-up events due to automotive transients or EMI. In Sleep Mode the INH pin is left floating. The internal termination between pin LIN and pin VS is disabled. Only a weak pull-up current (typical 10 A) between pin LIN and pin VS is present. The Sleep Mode can be activated independently from the actual level on pin LIN or WAKE. 3. Fail-safe Mode At system power-up or after a wake-up event, the device automatically switches to Failsafe Mode. It switches the INH pin to a high state, to the VS level. LIN communication is switched off. The microcontroller of the application will then confirm the Normal Mode by setting the EN pin to high. 4. Unpowered Mode If you connect battery voltage to the application circuit, the voltage at the VS pin increases according to the block capacitor. After VS is higher than the VS undervoltage threshold VSth, the IC mode changes from Unpowered Mode to Fail-safe Mode. Figure 3-1. Mode of Operation
Unpowered Mode VBatt = 0V a: VS > 5V b: VS < 5V c: Bus wake-up event d: Wake-up from wake switch
b
a
Fail-safe Mode INH: high (INH internal high-side switch ON) Communication: OFF b
b
c EN = 1 d Go to sleep command EN = 0; after 1 0 while TXD = 1 Normal Mode INH: high (INH HS switch ON) Communication: ON Local wake-up event EN = 1 Sleep Mode INH: high impedance (INH HS switch OFF) Communication: OFF
Table 3-1.
Table of Modes
Transceiver Off On Off INH On On Off RXD High, except after wake up LIN depending High ohmic LIN Recessive TXD depending Recessive
Mode of Operation Fail-safe Normal Sleep
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Wake-up events from Sleep Mode: * LIN bus * EN pin * WAKE pin * VS Undervoltage Figure 3-1 on page 5, Figure 3-2 on page 6 and Figure 3-3 on page 7 show details of wake-up operations.
3.12
Remote Wake-up via Dominant Bus State
A voltage less than the LIN pre-wake detection VLINL at pin LIN activates the internal LIN receiver and switches on the internal slave termination between the LIN pin and the VS pin. A falling edge at pin LIN, followed by a dominant bus level VBUSdom maintained for a certain time period (tBUS) and a rising edge at pin LIN results in a remote wake-up request. The device switches to Fail-safe Mode. Pin INH is activated (switches to VS) and the internal termination resistor is switched on. The remote wake-up request is indicated by a low level at pin RXD to interrupt the microcontroller (see Figure 3-2 on page 6).
Figure 3-2.
LIN Wake-up Waveform Diagram
Bus wake-up filtering time (tBUS) LIN bus
INH Low or floating
High
RXD
High or floating Low
External voltage regulator
Off state Regulator wake-up time delay Normal Mode EN High Node in sleep state Microcontroller start-up delay time
EN
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3.13 Local Wake-up via Pin WAKE
A falling edge at pin WAKE, followed by a low level maintained for a certain time period (tWAKE), results in a local wake-up request. The wake-up time (tWAKE) ensures that no transient, according to ISO7637, creates a wake-up. The device switches to Fail-safe Mode. Pin INH is activated (switches to VS) and the internal termination resistor is switched on. The local wake-up request is indicated by a low level at pin RXD to interrupt the microcontroller and a strong pull-down at pin TXD (see Figure on page 9). The voltage threshold for a wake-up signal is 3V below the VS voltage with an output current of typical -3 A. Even in the case of a continuous low at pin WAKE it is possible to switch the IC into Sleep Mode via a low at pin EN. The IC will stay in Sleep Mode for an unlimited time. To generate a new wake up at pin WAKE it needs first a high signal > 6 s before a negative edge starts the wake-up filtering time again. Figure 3-3. Wake-up from Wake-up Switch
Wake pin State change
INH
Low or floating
High
RXD
High or floating Low High
TXD
TXD weak pull-down resistor Wake filtering time tWAKE
TXD strong pull-down
Weak pull-down
Voltage regulator
On state Off state Node in operation EN High Node in sleep state Microcontroller start-up delay time
Regulator wake-up time delay EN
3.14
Wake-up Source Recognition
The device can distinguish between a local wake-up request (pin WAKE) and a remote wake-up request (LIN bus). The wake-up source can be read on pin TXD in Fail-safe Mode. If an external pull-up resistor (typically 5 k) has been added on pin TXD to the power supply of the microcontroller, a high level indicates a remote wake-up request (weak pull-down at pin TXD) and a low level indicates a local wake-up request (strong pull-down at pin TXD). The wake-up request flag (signalled on pin RXD) as well as the wake-up source flag (signalled on pin TXD) are reset immediately if the microcontroller sets pin EN to high (see Figure 3-2 on page 6 and Figure 3-3 on page 7).
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3.15
Fail-safe Features
* The reverse current is < 2 A at pin LIN during loss of VBAT; this is optimal behavior for bus systems where some slave nodes are supplied from battery or ignition. * Pin EN provides a pull-down resistor to force the transceiver into Sleep Mode if EN is disconnected. * Pin RXD is set floating if VBAT is disconnected. * Pin TXD provides a pull-down resistor to provide a static low if TXD is disconnected. * The LIN output driver has a current limitation, and if the junction temperature Tj exceeds the thermal shut-down temperature Toff, the output driver switches off. * The implemented hysteresis, Thys, enables the LIN output again after the temperature has been decreased.
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4. Absolute Maximum Ratings
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Parameters VS - Continuous supply voltage Wake DC and transient voltage (with 33-k serial resistor) - Transient voltage due to ISO7637 (coupling 1 nF) Logic pins (RXD, TXD, EN) LIN - DC voltage - Transient voltage due to ISO7637 (coupling 1 nF) INH - DC voltage ESD according to IBEE LIN EMC Test specification 1.0 following IEC 61000-4-2 - Pin VS, LIN to GND - Pin WAKE (33 k serial resistor) ESD HBM following STM5.1 with 1.5 k/100 pF - Pin VS, LIN, WAKE, INH to GND HBM ESD ANSI/ESD-STM5.1 JESD22-A114 AEC-Q100 (002) CDM ESD STM 5.3.1 Machine Model ESD AEC-Q100-RevF(003) Junction temperature Storage temperature Tj Tstg Symbol Min. -0.3 -1 -150 -0.3 -27 -150 -0.3 Typ. Max. +40 +40 +100 +5.5 +40 +100 VS + 0.3 Unit V V V V V V V
6 5
KV KV
6 3
KV KV
750 100 -40 -55 +150 +150
V V C C
5. Thermal Characteristics
Parameters Thermal resistance junction ambient Special heat sink at GND (pin 5) on PCB (fused lead frame to pin 5) Thermal shutdown Thermal shutdown hysteresis Symbol RthJA RthJA Toff Thys 150 5 80 165 10 180 20 Min. Typ. Max. 145 Unit K/W K/W C C
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6. Electrical Characteristics
5V < VS < 27V, Tj = -40C to +150C No. 1 1.1 1.2 Parameters VS Pin DC voltage range nominal Supply current in Sleep Mode Sleep Mode VLIN > VS - 0.5V VS < 14V Bus recessive VS < 14V Supply current in Normal Mode 1.4 Bus dominant VS < 14V Total bus load > 500 Bus recessive VS < 14V 7 7 VS IVSsleep IVSrec IVSdom IVSfail VSth VSth 7 VSth_hys 0.5 4 4.05 50 5 13.5 10 27 20 V A A A Test Conditions Pin Symbol Min. Typ. Max. Unit Type*
1.3
7
0.9
1.3
mA
A
7
1.2
2
mA
A
1.5 1.6 1.7 1.8 2 2.1 2.2 2.3 2.4 3 3.1 3.2 3.3 3.4 3.5 4 4.1 4.2 4.3 4.4 5 5.1 5.2
Supply current in Fail-safe Mode VS undervoltage threshold on VS undervoltage threshold off VS undervoltage threshold hysteresis RXD Output Pin (Open Drain) Low-level output sink current RXD saturation voltage High-level leakage current ESD zener diode TXD Input Pin Low-level voltage input High-level voltage input Pull-down resistor Low-level leakage current Low-level output sink current EN Input Pin Low-level voltage input High-level voltage input Pull-down resistor Low-level input current INH Output Pin High-level voltage Leakage current
7
1.1 4.95 5 500
mA V V mV
A A A A
Normal Mode VLIN = 0V, VRXD = 0.4V 5-k pull-up resistor to 5V Normal Mode VLIN = VBAT, VRXD = 5V IRXD = 100 A
1 1 1 1 4 4
IRXDL VsatRXD IRXDH VZRXD VTXDL VTXDH RTXD ITXD_leak ITXD
1.3
2.5
8 0.4
mA V A V V V k A mA
A A A A A A A A A
-3 5.8 -0.3 2 125 -3 1.3 2.5 250
+3 8.6 +0.8 5.5 600 +3 8
VTXD = 5V VTXD = 0V Fail-safe Mode, local wake up VTXD = 0.4V VLIN = VBAT
4 4 4
2 2 VEN = 5V VEN = 0V Normal Mode IINH = -2 mA Sleep Mode VINH = 0V/27V, VS = 27V 2 2
VENL VENH REN IEN
-0.3 2 125 -3 250
+0.8 5.5 600 +3
V V k A
A A A A
8 8
VINHH IINHL
VS - 3 -3
VS +3
V A
A A
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
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6. Electrical Characteristics (Continued)
5V < VS < 27V, Tj = -40C to +150C No. 6 6.1 6.2 6.3 6.4 7 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 Parameters WAKE Pin High-level input voltage Low-level input voltage Wake pull-up current High-level leakage current LIN Bus Driver Driver recessive output voltage Driver dominant voltage VBUSdom_DRV_LoSUP Driver dominant voltage VBUSdom_DRV_HiSUP Driver dominant voltage VBUSdom_DRV_LoSUP Driver dominant voltage VBUSdom_DRV_HiSUP Pull-up resistor to VS Voltage drop at the serial diodes LIN current limitation VBUS = VBAT_max Input leakage current at the receiver, including pull-up resistor as specified Input leakage current Driver off VBUS = 0V, VS = 12V Driver off 8V < VBAT < 18V 8V < VBUS < 18V VBUS VBAT RLOAD = 500 / 1 k VVS = 7V, Rload = 500 VVS = 18V, Rload = 500 VVS = 7V, Rload = 1000 VVS = 18V, Rload = 1000 The serial diode is mandatory In pull-up path with Rslave ISerDiode = 10 mA 6 6 6 6 6 6 6 6 VBUSrec V_LoSUP V_HiSUP V_LoSUP_1k V_HiSUP_1k_ RLIN VSerDiode IBUS_LIM IBUS_PAS_dom 0.6 0.8 20 0.4 40 120 30 60 1.0 200 0.9 x VS VS 1.2 2 V V V V V k V mA A A A A A A D A IWAKE = Typically -3 A VS < 27V VS = 27V, VWAKE = 27V 3 3 3 3 VWAKEH VWAKEL IWAKE IWAKE VS - 1V -1V -30 -5 -10 +5 VS + 0.3V VS - 3.3V V V A A A A A A Test Conditions Pin Symbol Min. Typ. Max. Unit Type*
7.9
6
-1
mA
A
7.10
Leakage current LIN recessive
6
IBUS_PAS_rec
10
20
A
A
7.11
Leakage current at ground loss; Control unit disconnected from GNDDevice = VS ground; Loss of local ground VBAT =12V must not affected communication 0V < VBUS < 18V in the residual network Leakage current at loss of battery; Node has to substain the VBAT disconnected current that can flow under this VSUP_Device = GND 0V < VBUS < 18V condition; Bus must remain operational under this condition Capacitance on pin LIN to GND
6
IBUS_NO_gnd
-10
+0.5
+10
A
A
7.12
6
IBUS_NO_bat
0.1
2
A
A
7.13
6
CLIN
20
pF
D
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
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6. Electrical Characteristics (Continued)
5V < VS < 27V, Tj = -40C to +150C No. 8 8.1 8.2 8.3 8.4 8.5 8.6 9 9.1 9.2 Parameters LIN Bus Receiver Center of receiver threshold Receiver dominant state Receiver recessive state Receiver input hysteresis Pre-wake detection LIN High-level input voltage Pre-wake detection LIN Low-level input voltage Internal Timers Dominant time for wake-up via LIN bus Time of low pulse for wake-up via pin WAKE Time delay for mode change from Fail-safe Mode to Normal Mode via pin EN Time delay for mode change from Normal Mode into Sleep Mode via pin EN TXD dominant time out time VLIN = 0V VWAKE = 0V VEN = 5V 6 3 tBUS tWAKE tnorm 30 7 90 35 150 50 s s A A Switches the LIN receiver on VBUS_CNT = (Vth_dom + Vth_rec) / 2 VEN = 5V VEN = 5V VHYS = Vth_rec - Vth_dom 6 6 6 6 6 6 VBUS_CNT VBUSdom VBUSrec VBUShys VLINH VLINL 0.475 x VS -27 0.6 x VS 0.028 x VS VS - 2V -27V 0.1 x VS 0.5 x VS 0.525 x VS 0.4 x VS 40 0.175 x VS VS + 0.3V VS - 3.3V V V V V V V A A A A A A Test Conditions Pin Symbol Min. Typ. Max. Unit Type*
9.3
2
2
7
15
s
A
9.4 9.5 9.6
VEN = 0V VTXD = 0V
2 4
tsleep tdom tVS
2 6
7 9
12 20 200
s ms s
A A A
Power-up delay between VS = 5V VVS = 5V until INH switches to high
10
LIN Bus Driver AC Parameter with Different Bus Loads Load 1 (small): 1 nF, 1 k ; Load 2 (large): 10 nF, 500 ; RRXD = 5 k ; CRXD = 20 pF; Load 3 (medium): 6.8 nF, 660 characterized on samples; 10.1 and 10.2 specifies the timing parameters for proper operation at 20 Kbit/s, 10.3 and 10.4 at 10.4 Kbit/s. THRec(max) = 0.744 x VS THDom(max) = 0.581 x VS VS = 7.0V to 18V tBit = 50 s D1 = tbus_rec(min) / (2 x tBit) THRec(min) = 0.422 x VS THDom(min) = 0.284 x VS VS = 7.0V to 18V tBit = 50 s D2 = tbus_rec(max) / (2 x tBit) THRec(max) = 0.778 x VS THDom(max) = 0.616 x VS VS = 7.0V to 18V tBit = 96 s D3 = tbus_rec(min) / (2 x tBit)
10.1
Duty cycle 1
6
D1
0.396
A
10.2
Duty cycle 2
6
D2
0.581
A
10.3
Duty cycle 3
6
D3
0.417
A
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
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6. Electrical Characteristics (Continued)
5V < VS < 27V, Tj = -40C to +150C No. Parameters Test Conditions THRec(min) = 0.389 x VS THDom(min) = 0.251 x VS VS = 7.0V to 18V tBit = 96 s D4 = tbus_rec(max) / (2 x tBit) Pin Symbol Min. Typ. Max. Unit Type*
10.4
Duty cycle 4
6
D4
0.590
A
11 11.1
Receiver Electrical AC Parameters of the LIN Physical Layer LIN receiver, RXD load conditions: CRXD = 20 pF, Rpull-up = 5 k Propagation delay of receiver (see Figure 6-1 on page 13) Symmetry of receiver propagation delay rising edge minus falling edge trec_pd = max(trx_pdr, trx_pdf) VS = 7.0V to 18V trx_sym = trx_pdr - trx_pdf VS = 7.0V to 18V 1 trx_pd trx_sym -2 6 s A
11.2
1
+2
s
A
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Figure 6-1.
Definition of Bus Timing Parameter
tBit tBit tBit
TXD (Input to transmitting node)
tBus_dom(max)
tBus_rec(min)
THRec(max) VS (Transceiver supply of transmitting node) THDom(max) LIN Bus Signal THRec(min) THDom(min)
Thresholds of receiving node 1
Thresholds of receiving node 2
tBus_dom(min) RXD (Output of receiving node 1) trx_pdf(1)
tBus_rec(max)
trx_pdr(1)
RXD (Output of receiving node 2) trx_pdr(2) trx_pdf(2)
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Figure 6-2.
Application Circuit
Master node pull-up
VBATTERY
22 F
100 nF 12V 5V 1k
VDD
5 k
ATA6662
1 Receiver
VS
RXD
Microcontroller
Filter
6 LIN
Wake-up bus timer 4 TXD GND IO VS 10 k 33 k External switch WAKE 3 Wake-up timer TXD Time-out timer Slew rate control
Short-circuit and overtemperature protection 220 pF
VS Control unit Sleep mode 5 GND 2 EN 8 INH
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LIN sub bus
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7. Ordering Information
Extended Type Number ATA6662-TAQY ATA6662C-TAQY Package SO8 SO8 Remarks LIN transceiver, Pb-free, 4k, taped and reeled LIN transceiver, Pb-free, 4k, taped and reeled
8. Package Information
Package: SO 8 Dimensions in mm 4.90.1 50.2 3.70.1
0.2
0.1+0.15
1.4
0.4 1.27 3.81
3.80.1 60.2
8
5
technical drawings according to DIN specifications
1 Drawing-No.: 6.541-5031.01-4 Issue: 1; 15.08.06
4
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9. Revision History
Please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this document. Revision No. 4916O-AUTO-05/10 History * Features on page 1 changed * Heading 3.6: text changed * * * * Features on page 1 changed Section 4 "Absolute Maximum Ratings" on page 9 changed Section 6 "Electrical Characteristics" number 7.13 on page 11 added Section 7 "Ordering Information" on page 16 changed
4916N-AUTO-03/10
4916M-AUTO-09/09 4916L-AUTO-02/09
* Figure 1-1 "Block Diagram" on page 1 changed * Section 4 "Absolute Maximum Ratings" on page 8 changed * Figure 6-2 "Application Circuit" on page 14 changed * Section 6 "El.Characteristics" numbers 3.2 and 4.2 on page 9 changed * * * * * * * * * * * * * * * * Figure 2-1 "Pinning SO8" on page 2 changed Section 3.2 "Supply Pin (VS)" on page 3 changed Section 3.8 "Enable Input Pin (EN)" on page 4 changed Section 3.11 "Operation Modes" on page 5 changed Section 3.12 "Remote Wake-up via Dominant Bus State" on page 5 changed Section 3.14 "Wake-up Source Recognition" on page 6 changed Figure 3.2 "LIN Wake-up Waveform Diagram" on page 7 changed Figure 3.3 "Wake-up from Wake-up Switch" on page 7 changed Section 4 "Absolute Maximum Ratings" on page 8 changed Section 5 "Thermal Resistance" on page 8 changed Section 6 "Electrical Characteristics" on pages 9 to 12 changed Figure 6-2 "Application Circuit" on page 13 changed "Pre-normal Mode" in "Fail-safe Mode" changed Section 3.9 "Inhibit Output Pin (INH) on page 4 changed Section 4 "Absolute Maximum Ratings" on page 8 changed Section 6 "Electrical Characteristics" number 5.1 on page 9 changed
4916K-AUTO-12/08
4916J-AUTO-02/08
4916I-AUTO-12/07 4916H-AUTO-10/07 4916G-AUTO-07/07
* Section 3.1 "Physical Layer Compatibility" on page 3 added * Section 6 "El.Characteristics" numbers 1.5, 1.6 and 1.7 on page 9 changed * Section 7 "Ordering Information" on page 14 changed * Put datasheet in a new template * Capital T for time generally changed in a lower case t
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Please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this document. (Continued) Revision No. History * * * * Figure 1-1 "Block Diagram" on page 1 changed Figure 6-2 "Application Circuit" on page 13 changed Features on page 1 changed Section 6 "El.Characteristics" numbers 10.1 to 10.4 and 11.1, 11.2 changed
4916F-AUTO-05/07
4916E-AUTO-02/07
* Section 4 "Absolute Maximum Ratings" on page 8 changed * Section 2 "Electrical Characteristics" on pages 9 to 11 changed * * * * * * * * * * Features on page 1 changed Section 1 "Description" on page 1 changed Table 2-1 "Pin Description" on page 2 changed Section 3.2 "Ground Pin (GND) on page 3 changed Section 3.7 "Enable Input Pin (EN)" on page 4 changed Section 3.11 "Remote Wake-up via Dominant Bus State" on page 5 changed Figure 3-1 "Mode of Operation" on page 6 changed Section 3-14 "Fail-safe Features" on page 6 changed Section 4 "Absolute Maximum Ratings" on page 8 changed Section 6 "Electrical Characteristics" on pages 9 to 11 changed
4916D-AUTO-02/07
17
4916O-AUTO-05/10
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4916O-AUTO-05/10

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